1. Field of the Invention
The present invention generally relates to a method of fabricating a resistance memory, and more particularly, to a method of fabricating a variable resistance layer of a resistance memory.
2. Description of Related Art
The resistance memory is a memory based on the resistive state thereof for writing data. Since the resistance memory is advantageous in compatibility with the process for complementary metal oxide semiconductor transistor (CMOS transistor), simple structure, small size, fast operation speed and low electricity-consumption, it has become a popular non-volatile memory currently.
A resistance memory 100 is usually shown as FIG. 1, which includes an upper electrode 102, a lower electrode 104 and a variable resistance layer 106 located between the upper electrode 102 and the lower electrode 104, so that the resistance memory 100 has a sandwich structure of metal-insulation-metal (MIM). The resistance value (or resistive state) of the resistance memory 100 can be controlled to a high resistive state (HRS or termed as “insulation state”) and a low resistive state (LRS or termed as “conductive state”) by adjusting the voltage applying between the upper electrode 102 and the lower electrode 104. The appropriate material to make the variable resistance layer 106 includes, for example, organic macromolecule material, solid-state electrolyte, calcium-titanium mineral material or oxide at present.
If silicon oxide (SiO2) is selected as the major component of a resistance layer, an additional metal component, for example, copper (Cu), is required to add in, so that the switch between HRS and LRS can be achieved. The method of adding copper into the SiO2 layer currently is mostly to plate copper onto the SiO2 layer, followed by annealing in high-temperature (higher than 500° C.) so as to allow copper to thermally diffuse into the SiO2 layer as described in Schindler et al, IEEE Transactions on Electron Devices, Vol. 54, No. 10, pp. 2762-2768 (2007).
However, the above-mentioned method to fabricate a Cu—SiO2 variable resistance layer requires at least two steps after forming the SiO2 layer. In addition, the diffusion procedure needs a very high temperature, so that the above-mentioned method is not ideal in terms of the fabricating period and the cost (energy consumption).